IQIM Postdoctoral and Graduate Student Seminar

Note: this week's talk is in 310 Linde Hall (Math Building, third floor)

Abstract: In order to solve problems of practical importance, quantum computers will likely need to incorporate quantum error correction, where a logical qubit is redundantly encoded in many noisy physical qubits. Quantum error correction typically incurs large physical qubit overheads, motivating the search for more hardware-efficient approaches. In this talk we will discuss a superconducting circuit which realizes a logical qubit memory formed from the concatenation of encoded bosonic cat qubits with an outer repetition code of distance d=5. The bosonic cat qubits are passively protected against bit flips by two photon dissipation. Cat-qubit phase-flip errors are corrected by a repetition code which uses ancilla transmons for syndrome measurement. We will discuss the architecture we use for syndrome measurements and characterize the performance of the logical qubit memory. The phase-flip correcting repetition code operates below threshold, with logical phase-flip error decreasing with code distance from d=3 to d=5. Concurrently, the logical bit-flip error is suppressed with increasing cat-qubit mean photon number. The minimum measured logical error per cycle is on average 1.75(2)% for the distance-3 code sections, and 1.65(3)% for the longer distance-5 code, demonstrating the effectiveness of bit-flip error suppression throughout the error correction cycle. We will tie our results to the longer term opportunities for reaching computationally relevant error rates with concatenated bosonic qubits.

Lunch will be provided outside the Bridge building, following the talk.